In present-day systems on chips (commonly known by the acronym SOC for “System on Chip”), the aging of the electronic components is anticipated in the design of said systems.
Aging is usually compensated by supplementing the supply voltage with an excess, or compensation, voltage, so that aged components continue to operate satisfactorily in a “used” product. For example, an excess of 40 mV for a power supply of 150 mV is usually provided after the initial use of such a system on a chip.
This compensation therefore results in excess energy consumption after the initial use, which is a drawback in applications where energy efficiency is prized, for example in the case of a weak battery or where the aim is to minimize energy loss.
This loss of performance may be even more serious if the same design of a system on a chip is used for different mission profiles. A mission profile is a model of use corresponding to various constraints that will affect the system on a chip. By way of illustration, a system designed for industry will be more intensively used than a system designed for a car, which will itself be more intensively used than a system used by private individuals.
The systems on chips that can be used in various mission profiles are therefore designed to withstand the most constraining model, and this represents a loss of competitiveness because there is poor compliance with the conventional energy values (referred to as PPA for “Power Purchase Agreement”) for less constraining mission profiles.
Thus, the systems for managing the aging of electronic components present a problem of power supply optimization, in a compromise between performance and reliability, allowance being made for the limitations of systems on chips including said components.
It would therefore be desirable to resolve this problem by providing adaptive compensation for the aging of systems on chips.
Regarding the adaptive adjustment of the voltage and frequency of a system on a chip, U.S. Pat. No. 8,154,335 (incorporated by reference) describes a system on a chip in which a supply voltage is reduced and/or a clock frequency is increased in order to provide conditions of use within acceptable margins, said margins being generated by a critical path replica circuit. This prior art system also describes an increase in the voltage and/or a reduction in the frequency for preventive purposes if said acceptable operating margins of the conditions of use are exceeded.
The solution proposed in U.S. Pat. No. 8,154,335 is adapted to occasional variations in the operation of the system on a chip, but does not make allowance for the aforementioned long-term problems of excess power supply and aging.